1. Field of the Invention
The present invention relates to a non-volatile semiconductor storage device, more particularly to an electrically writable non-volatile semiconductor storage such as an EPROM and a flash memory.
2. Description of the Related Art
An EPROM, a flash memory, or the like is known as an electrically writable non-volatile semiconductor storage device. A writing voltage to be applied to memory cells in such non-volatile semiconductor storage device is approximately 6 to 7 V. Each of the memory cells comprises a transistor having floating gates. Injection of electrons to the floating gates causes data writing. This data writing structure requires such relatively high writing voltage.
There are two ways for obtaining a high voltage for writing, external supply and internal boost.
In the former way, the high voltage is supplied to a special power pin of a non-volatile semiconductor storage device. The special power pin is designed in addition to a normal power pin exclusively for high voltage supply.
In the latter way, a boost circuit in a non-volatile semiconductor storage device boosts a voltage supplied as a normal power source. The amount of supplied current for the data writing depends on the current supply ability of the booster. Generally, the amount of the current obtained with the internal boosting way is smaller than that obtained with the external supplying way. Because of this, the number of memory cells which can accept the data writing at a time is also smaller. In case of the number of the memory cells which can accept the data writing per an access is large such as eight or sixteen, a bit line in a memory device is usually divided into a plurality of groups in accordance with the current supply ability of its own booster. In such memory device, the data writing is performed group by group.
FIG. 12 shows a conventional non-volatile semiconductor storage device 1400 which writes data divisionally. The number of memory cells which can accept the data writing at a time in the non-volatile semiconductor storage device 1400 is sixteen. That is, data (16-bit data) can be written/read to/from the sixteen cells per an access. The non-volatile semiconductor storage device 1400 comprises a memory cell array 1402 having a plurality of non-volatile memory cells, a row decoder 1404 and a column switches 1406. The column switches include four column switches 1406-0, 1406-1, 1406-2 and 1406-3.
Each of these column switches 1406-0, 1406-1, 1406-2 and 1406-3 selects four bit lines on the basis of column address AYn. The selected bit lines are connected to corresponding data writing circuits 1412-0, 1412-1, 1412-2 and 1412-3 via data lines DL0 to DL15 and data writing lines WD0 to WD15.
The data writing circuits 1412 receives data rewriting flags from verifying circuits 1414 and a pulse signal PLS from the writing pulse generating circuit 1418. The wiring circuits 1412 supplies a writing voltage Vpump, which is supplied from a writing voltage generating circuit 1410, to the corresponding data writing lines WD0 to WD15 on the basis of the flags and the pulse signal PLS.
An operation of the non-volatile semiconductor storage device 1400 will now be described with reference to FIG. 13.
The writing voltage generating circuit 1410 is activated in response to an externally supplied data writing command (step 1500) to generate the writing voltage Vpump (step 1502). Then, the writing voltage generating circuit 1410 receives an address signal from an address pin (not shown) and accesses address to be written. The writing voltage generating circuit 1410 reads data from the accessed address and supplies it to the verifying circuits 1414 via the data lines DL0 to DL15. The verifying circuits 1414 compare writing data from a data pin (not shown) with the read data (step 1504).
When the read data completely coincide with the writing data (the result of step 1504 is "PASS"), the writing operation is terminated (step 1516). If the coincidence of those is incomplete, it is determined that the verification is failed (the result of step 1504 is "FAIL"), and further sequential steps for writing (described later) are executed for rewriting the data.
"Data writing" in this specification means to switch the mode of the memory cells from erase mode to write mode. Counter switching action is not included in the meaning of "data writing". For example, if the modes of the memory cells are digitized, "1" denotes the memory cell in the erase mode and "0" denotes the memory cell in the write mode. "Write" means to switch "1" to "0", and "erase" means to switch "0" to "1".
After the verifying circuits 1414 detect that the read data do not coincide with the writing data, the verifying circuits 1414 select target memory cells for the data writing from the accessed sixteen memory cells. Then the verifying circuits 1414 activates the data rewriting flags FL0 to FL15, and output the flags to the data writing circuit 1412 (step 1506).
Of the data writing circuits 1412, a data writing circuit 1412-0 corresponds to first 4 bits in the 16-bit data. In response to the writing pulse signal PLS, the data writing circuit 1412-0 supplies the writing voltages vpump to the data writing lines WD0 to WD3 corresponding to the activated data rewriting flags FL0 to FL3 (step 1508). Data writing circuits 1412-1, 1412-2 and 1412-3 sequentially perform the data writing operations in the same manner. Thus, a first cycle of the data writing is completed (steps 1510, 1512 and 1514).
The writing voltage generating circuit 1410 can supply the currents to four memory cells (maximum) per a data writing operation. In other words, the writing voltage generating circuit 1410 does not have the ability to supply currents to sixteen memory cells at a time. Therefore, the non-volatile semiconductor storage device comprises four data writing circuits 1412 and the data writing cycle has four installments of the data writing operations as described above.
After the data writing operation in the first cycle is completed, data stored in the sixteen memory cells are read again. Then the read data is compared with the writing data (step 1504).
When complete coincidence of the both data is detected, the data writing operation is terminated (step 1516). If the coincidence is still incomplete, the sequential data writing steps are executed again because the data writing so far is incomplete. This process is repeated until the complete coincidence of the both data is detected.
As described, the above process includes only the data writing operations without data erasing operations. Therefore, even if the writing data is "1010" which corresponds to, for example, 4 bits data "1100" of 16-bit data for the data writing, the resultant data is "1000". In this case, the data to be written does not coincide with actuary written data even if the data writing operations are repeated. The management for such case depends on the specification of a memory device. Generally, a flag indicating exceeds of retrial times is set to display that the data to be written does not coincide with the actual written data. The management for the activation of such flag also depends on the specification of a memory device.
However, a data rewriting operation requiring the erasing operation seldom occurs usually. Therefore, the flag indicating the exceeds of retrial times is seldom activated.
In the above described conventional non-volatile semiconductor storage device 1400, data to be written is previously divided into four parts for four installments of the writing operations in accordance with the ability of the writing voltage generating circuit 1410. Thus, in spite of the number of the memory cells, the data writing operation must be performed four times. In other words, the four-time data writing operation is required for not only 16-bit data writing but also 1-bit data writing. Therefore, time required for the 1-bit data writing is the same as that for the 16-bit data writing.